1. Field of the Invention
The present invention generally relates to the field of metal-oxide-semiconductor (MOS) transistors, and more particularly, to a method for forming MOS transistors having strained silicon.
2. Description of the Prior Art
A metal-oxide-semiconductor is a common electrical device used in integrated circuits. The MOS transistor is a semiconductor component, usually formed by a gate, a source and a drain. By utilizing channel effects generated by the gate of the MOS under different gate voltages, the MOS is often made to function as a digitalized solid switch applied on various integrated circuits of memory or logic devices.
Please refer to FIGS. 1-3, where FIGS. 1-3 are schematic diagrams illustrating a prior art method of fabricating a MOS transistor. As shown in FIG. 1, a semiconductor substrate 10 is first prepared. A gate dielectric layer 14 and a gate 12 positioned on the dielectric layer 14 are formed on the semiconductor substrate 10, where the gate dielectric layer 14 and the gate 12 form a gate structure. Subsequently, a shallow-junction source extension 17 and a shallow-junction drain extension 19 are formed within the semiconductor substrate 10 on the opposite sides of the gate structure 12. The shallow-junction source extension 17 and the shallow-junction drain extension 19 are separated by a channel region 22 of the MOS transistor. For an N-type metal-oxide-semiconductor (NMOS) transistor, the dopant species of the shallow-junction source extension 17 and the shallow-junction drain extension 19 may be N-type dopant species, such as arsenic, antimony or phosphorous. Next, a liner 30 and a spacer 32 are formed around the sidewall of the gate 12.
As shown in FIG. 2, an ion implantation process is afterward carried out to implant dopants into the semiconductor substrate 10. Accordingly, a source region 18 and a drain region 20 are formed on opposite sides of the gate 12 within the semiconductor structure 10, thereby forming a MOS transistor 34. As mentioned above, the dopant species may be N-type dopant species, such as arsenic, antimony or phosphorous, for the NMOS transistor.
Furthermore, as shown in FIG. 3, a stressed cap layer 46 is formed to cover the surface of the MOS transistor 34. The stressed cap layer 46 consists mainly of silicon nitride, and the thickness of the stressed cap layer 46 is in a range from 10 angstroms to 3000 angstroms so as to provide a tensile stress on the MOS transistor 34. Next, an activating process is performed on the stressed cap layer 46 to make the MOS transistor 34 memorize the stress and at the same time to expand the lattice arrangement in the channel region 22 of the semiconductor substrate 10 underneath the gate dielectric layer 14.
As known to those skilled in this art, higher the stress of the stressed cap layer 46 is, more effectively the stress of the stressed cap layer 46 can expand the lattice arrangement in the channel region 22 of the semiconductor substrate 10. Accordingly, the ion gain of the MOS transistor 34 should be increased as well. However, the stress of the stressed cap layer 46 might crack or break the structure of the MOS transistor 34 in fact when the stress of the stressed cap layer 46 goes beyond a limit. Thereafter, the function of the stressed cap layer 46 is a lot defeated, and the ion gain of the MOS transistor 34 is smaller than the expected ion gain.
Please refer to FIG. 4 and FIG. 5, where FIG. 4 is a schematic chart illustrating a relationship between the tensile stress of the prior art stress cap layer 46 and the ion gain of the prior art MOS transistor 34, and FIG. 5 is a cross-sectional schematic diagram illustrating the prior art stress cap layer 46 having a high tensile stress. As shown in FIG. 4, when the tensile stress of the stressed cap layer 46 is below 1.52 Giga pascals (GPa), the ion gain of the MOS transistor 34 is mainly proportional to the tensile stress of the stress cap layer 46. When the tensile stress of the stressed cap layer 46 goes beyond 1.52 GPa, the ion gain difference is relatively smaller under the same tensile stress difference. When the tensile stress of the stressed cap layer 46 goes beyond 1.65 GPa, cracks appear commonly in the stress cap layer 46 structure, and the ion gain of the MOS transistor 34 decreases immediately. Therefore, the stressed cap layer 46 having tensile stress beyond 1.65 GPa is inferior to the stressed cap layer 46 having tensile stress about 1.60 Gpa. As shown in FIG. 5, when the tensile stress of the stressed cap layer 46 is approximately 1.65 GPa, cracks appear in the stress cap layer 46 structure. Since the stressed cap layer 46 has turning points at the joints between the gate structure and the semiconductor substrate 10, the cracks likely appear at the turning points, and defeat the operating efficiency of the MOS transistor 34.